NVM Design and Technology is an organization that enables advanced Embedded Non-Volatile Memory (NVM) IPs used in all markets covered by NXP (Automotive, Industrial & IoT, Mobile and communication infrastructures). Our mission is to deliver best-in-class NVM IPs that enable NXP next generation products across the various technology nodes used in the company. Our expertise covers multiple NVM technologies such as One-Time Programmable (OTP), Multi-Time Programmable (MTP), Flash, RRAM, MRAM in different technology nodes from advanced BCD processes to advanced FinFET nodes. You will be part of a highly skilled extended and cross-functional team of R&D engineers composed of Analog and Digital integrated circuit designers, as well as validation, test and reliability engineers. Your Responsibilities Specify the architecture of the digital controller, including self-test and security features. Perform the RTL design in Verilog Build testbenches to verify the functionality of the controller Run the entire digital design flow up to place and route to verify the physical implementation Write the design report to enable reuse What’s in it for you A great opportunity to develop your skills (technical, soft skills, communication, etc.) and experience the entire integrated circuit digital design flow Gaining experience in a multinational and diverse environment Possibility to become part of NXP’s Young Professional Talent Pool Working on real assignments which contribute to NXP’s objectives Your Profile Master of Science or Bachelor – last year of technical university or engineer school, electrical engineering with a strong grasp on digital circuit design. Affinity with Verilog/VHDL language and digital simulation tools. Affinity with Linux environment is a plus Ability to develop automation script and software is a plus Team player and eager to learn Good level of English is required (attendance to meetings / presentations with international team, reading and writing of documentation) More information about NXP in the Netherlands... #LI-3623